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msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 1 post office box 655303 ? dallas, texas 75265 low supply-voltage range, 1.8 v to 3.6 v ultralow-power consumption: ? active mode: 200 a at 1 mhz, 2.2 v ? standby mode: 0.7 a ? off mode (ram retention): 0.1 a five power-saving modes wake-up from standby mode in less than 6 s frequency-locked loop, fll+ 16-bit risc architecture, 125-ns instruction cycle time scan if for background water, heat, and gas volume measurement 16-bit timer_a with three capture/compare registers 16-bit timer_a with five capture/compare registers integrated lcd driver for up to 96 segments on-chip comparator serial onboard programming, no external programming voltage needed programmable code protection by security fuse brownout detector supply voltage supervisor/monitor with programmable level detection bootstrap loader in flash devices family members include: ? msp430fw423: 8kb + 256b flash memory, 256b ram ? msp430fw425: 16kb + 256b flash memory, 512b ram ? msp430fw427: 32kb + 256b flash memory, 1kb ram available in 64-pin quad flat pack (qfp) for complete module descriptions, refer to the msp430x4xx family user?s guide , literature number slau056 description the texas instruments msp430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mod e in less than 6 s. the msp430xw42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 lcd segment drive capability, a scan interface, and 48 i/o pins. typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. the comparator and timers make the configurations ideal for gas, heat, and water meters, industrial meters, counter applications, handheld meters, etc. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. these devices have limited built-in esd protection. please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 2007, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 2 post office box 655303 ? dallas, texas 75265 available options packaged devices t a plastic 64-pin qfp (pm) ?40 c to 85 c msp430fw423ipm msp430fw425ipm MSP430FW427IPM pin designation, msp430xw42x 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p1.5/ta0clk/aclk p6.2/sifch2 p6.1/sifch1 p6.0/sifch0 rst/nmi tck tms tdi/tclk tdo/tdi p1.0/ta0.0 p1.1/ta0.0/mclk p1.2/ta0.1 p1.3/ta1.0/svsout p1.4/ta1.0 p4.4/s5 p4.3/s6 p4.2/s7 p4.1/s8 p4.0/s9 p3.7/s10 p3.6/s11 p3.5/s12 p3.4/s13 p3.3/s14 p3.2/s15 p3.1/s16 p3.0/s17 p2.7/sifclkg/s18 p2.6/caout/s19 p2.5/ta1clk/s20 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p1.6/ca0 p1.7/ca1 p2.0/ta0.2 p2.1/ta1.1 p5.7/r33 p5.6/r23 p5.5/r13 r03 p5.4/com3 p5.3/com2 p5.2/com1 com0 p2.2/ta1.2/s23 p2.4/ta1.4/s21 p2.3/ta1.3/s22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p6.3/sifch3/sifcaout p6.4/sifci0 p6.5/sifci1 p6.6/sifci2/sifdacout p6.7/sifci3/svsin sifci xin xout sifvss sifcom p5.1/s0 p5.0/s1 p4.7/s2 p4.5/s4 p4.6/s3 msp430xw42x av cc dv ss av ss dv cc
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 3 post office box 655303 ? dallas, texas 75265 functional block diagram comparator_ a dv cc dv ss av cc av ss rst /nmi p2 flash 32kb 16kb 8kb ram 1kb 512b 256b watchdog timer wdt 15/16-bit port 2 8 i/o interrupt capability por/ multilevel svs/ brownout basic timer 1 1 interrupt vector lcd 96 segments 1,2,3,4 mux f lcd 8 mclk xout jtag interface xin smclk aclk mdb mab emulation p3 port 3 8 i/o 8 module timer1_a5 5 cc reg p1 port 1 8 i/o interrupt capability 8 p4 port 4 8 i/o 8 scan if oscillator fll+ 8 mhz cpu incl. 16 registers p5 port 5 8 i/o 8 p6 port 6 8 i/o 8 timer0_a3 3 cc reg
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description av cc 64 analog supply voltage, positive terminal. supplies svs, brownout, oscillator, comparator_a, scan if afe, port 6, and lcd resistive divider circuitry; must not power up prior to dv cc . av ss 62 analog supply voltage, negative terminal. supplies svs, brownout, oscillator, comparator_a, scan if afe. and port 6. must be externally connected to dv ss . internally connected to dv ss . dv cc 1 digital supply voltage, positive terminal. dv ss 63 digital supply voltage, negative terminal. sifvss 10 scan if afe reference supply voltage. p1.0/ta0.0 53 i/o general-purpose digital i/o/timer0_a. capture: cci0a input, compare: out0 output/bsl transmit p1.1/ta0.0/mclk 52 i/o general-purpose digital i/o/timer0_a. capture: cci0b input/mclk output/bsl receive note: ta0.0 is only an input on this pin. p1.2/ta0.1 51 i/o general-purpose digital i/o/timer0_a, capture: cci1a input, compare: out1 output p1.3/ta1.0/ svsout 50 i/o general-purpose digital i/o/timer1_a, capture: cci0b input/svs: output of svs comparator note: ta1.0 is only an input on this pin. p1.4/ta1.0 49 i/o general-purpose digital i/o/timer1_a, capture: cci0a input, compare: out0 output p1.5/ta0clk/ aclk 48 i/o general-purpose digital i/o/input of timer0_a clock/output of aclk p1.6/ca0 47 i/o general-purpose digital i/o/comparator_a input p1.7/ca1 46 i/o general-purpose digital i/o/comparator_a input p2.0/ta0.2 45 i/o general-purpose digital i/o/timer0_a, capture: cci2a input, compare: out2 output p2.1/ta1.1 44 i/o general-purpose digital i/o/timer0_a, capture: cci1a input, compare: out1 output p2.2/ta1.2/s23 35 i/o general-purpose digital i/o/timer1_a, capture: cci2a input, compare: out2 output/lcd segment output 23 (see note) p2.3/ta1.3/s22 34 i/o general-purpose digital i/o/timer1_a, capture: cci3a input, compare: out3 output/lcd segment output 22 (see note) p2.4/ta1.4/s21 33 i/o general-purpose digital i/o/timer1_a, capture: cci4a input, compare: out4 output/lcd segment output 21 (see note) p2.5/ta1clk/s20 32 i/o general-purpose digital i/o/input of timer1_a clock/lcd segment output 20 (see note) p2.6/caout/s19 31 i/o general-purpose digital i/o/comparator_a output/lcd segment output 19 (see note) p2.7/sifclkg/ s18 30 i/o general-purpose digital i/o/scan if, signal sifclkg from internal clock generator/lcd segment output 18 (see note) p3.0/s17 29 i/o general-purpose digital i/o/ lcd segment output 17 (see note) p3.1/s16 28 i/o general-purpose digital i/o/ lcd segment output 16 (see note) p3.2/s15 27 i/o general-purpose digital i/o/ lcd segment output 15 (see note) p3.3/s14 26 i/o general-purpose digital i/o/ lcd segment output 14 (see note) p3.4/s13 25 i/o general-purpose digital i/o/lcd segment output 13 (see note) p3.5/s12 24 i/o general-purpose digital i/o/lcd segment output 12 (see note) p3.6/s11 23 i/o general-purpose digital i/o/lcd segment output 11 (see note) p3.7/s10 22 i/o general-purpose digital i/o/lcd segment output 10 (see note) note: lcd function selected automatically when applicable lcd module control bits are set, not with pxsel bits.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 5 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description p4.0/s9 21 i/o general-purpose digital i/o/lcd segment output 9 (see note) p4.1/s8 20 i/o general-purpose digital i/o/lcd segment output 8 (see note) p4.2/s7 19 i/o general-purpose digital i/o/lcd segment output 7 (see note) p4.3/s6 18 i/o general-purpose digital i/o/lcd segment output 6 (see note) p4.4/s5 17 i/o general-purpose digital i/o/lcd segment output 5 (see note) p4.5/s4 16 i/o general-purpose digital i/o/lcd segment output 4 (see note) p4.6/s3 15 i/o general-purpose digital i/o/lcd segment output 3 (see note) p4.7/s2 14 i/o general-purpose digital i/o/lcd segment output 2 (see note) p5.0/s1 13 i/o general-purpose digital i/o/lcd segment output 1 (see note) p5.1/s0 12 i/o general-purpose digital i/o/lcd segment output 0 (see note) com0 36 o common output. com0?3 are used for lcd backplanes p5.2/com1 37 i/o general-purpose digital i/o/common output. com0?3 are used for lcd backplanes p5.3/com2 38 i/o general-purpose digital i/o/common output. com0?3 are used for lcd backplanes p5.4/com3 39 i/o general-purpose digital i/o/common output. com0?3 are used for lcd backplanes r03 40 i input port of fourth positive (lowest) analog lcd level (v5) p5.5/r13 41 i/o general-purpose digital i/o/input port of third most positive analog lcd level (v4 or v3) p5.6/r23 42 i/o general-purpose digital i/o/input port of second most positive analog lcd level (v2) p5.7/r33 43 i/o general-purpose digital i/o/output port of most positive analog lcd level (v1) p6.0/sifch0 59 i/o general-purpose digital i/o/scan if, channel 0 sensor excitation output and signal input p6.1/sifch1 60 i/o general-purpose digital i/o/scan if, channel 1 sensor excitation output and signal input p6.2/sifch2 61 i/o general-purpose digital i/o/scan if, channel 2 sensor excitation output and signal input p6.3/sifch3/ sifcaout 2 i/o general-purpose digital i/o/scan if, channel 3 sensor excitation output and signal input/scan if comparator output p6.4/sifci0 3 i/o general-purpose digital i/o/scan if, channel 0 signal input to comparator p6.5/sifci1 4 i/o general-purpose digital i/o/scan if, channel 1 signal input to comparator p6.6/sifci2/ sifdacout 5 i/o general-purpose digital i/o/scan if, channel 2 signal input to comparator/10-bit dac output p6.7/ sifci3/svsin 6 i/o general-purpose digital i/o/scan if, channel 3 signal input to comparator/svs, analog input sifci 7 i scan if input to comparator. sifcom 11 o common termination for scan if sensors. rst /nmi 58 i reset input or nonmaskable interrupt input port. tck 57 i test clock. tck is the clock input port for device programming and test. tdi/tclk 55 i test data input or test clock input. the device protection fuse is connected to tdi/tclk. tdo/tdi 54 i/o test data output port. tdo/tdi data output or programming data input terminal. tms 56 i test mode select. tms is used as an input port for device programming and test. xin 8 i input port for crystal oscillator xt1. standard or watch crystals can be connected. xout 9 o output terminal of crystal oscillator xt1. note: lcd function selected automatically when applicable lcd module control bits are set, not with pxsel bits.
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15 msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 6 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats; th e address modes are listed in table 2. table 1. instruction word formats dual operands, source-destination e.g. add r4,r5 r4 + r5 ???> r5 single operands, destination only e.g. call r8 pc ??>(tos), r8??> pc relative jump, un/conditional e.g. jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ??> r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5)??> m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ??> m(toni) absolute mov &mem,&tcdat m(mem) ??> m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ??> m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ??> r11 r10 + 2??> r10 immediate mov #x,toni mov #45,toni #45 ??> m(toni) note: s = source d = destination
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 7 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode (am) ? all clocks are active low-power mode 0 (lpm0) ? cpu is disabled aclk and smclk remain active, mclk is available to modules fll+ loop control remains active low-power mode 1 (lpm1) ? cpu is disabled aclk and smclk remain active, mclk is available to modules fll+ loop control is disabled low-power mode 2 (lpm2) ? cpu is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator remains enabled aclk remains active low-power mode 3 (lpm3) ? cpu is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator is disabled aclk remains active low-power mode 4 (lpm4) ? cpu is disabled aclk is disabled mclk, fll+ loop control, and dcoclk are disabled dco?s dc-generator is disabled crystal oscillator is stopped
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 8 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range 0ffffh ? 0ffe0h. the vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. interrupt source interrupt flag system interrupt word address priority power-up external reset watchdog flash memory wdtifg keyv (see note 1) reset 0fffeh 15, highest nmi oscillator fault flash memory access violation nmiifg ofifg accvifg (see notes 1 & 3) (non)maskable (non)maskable (non)maskable 0fffch 14 timer1_a5 ta1ccr0 ccifg (see note 2) maskable 0fffah 13 timer1_a5 ta1ccr1 ccifg to ta1ccr4 ccifg, ta1ctl taifg (see notes 1 & 2) maskable 0fff8h 12 comparator_a cmpaifg maskable 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 scan if sififg0 to sififg6 (see note 1) maskable 0fff2h 9 0fff0h 8 0ffeeh 7 timer0_a3 ta0ccr0 ccifg (see note 2) maskable 0ffech 6 timer0_a3 ta0ccr1 ccifg, ta0ccr2 ccifg, ta0ctl taifg (see notes 1 & 2) maskable 0ffeah 5 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 & 2) maskable 0ffe8h 4 0ffe6h 3 0ffe4h 2 i/o port p2 (eight flags) p2ifg.0 to p2ifg.7 (see notes 1 & 2) maskable 0ffe2h 1 basic timer1 btifg maskable 0ffe0h 0, lowest notes: 1. multiple source flags 2. interrupt flags are located in the module. 3. (non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 9 post office box 655303 ? dallas, texas 75265 special function registers most interrupt and module enable bits are collected into the lowest address space. special function register bits that are not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. interrupt enable 1 and 2 7654 0 ofie wdtie 321 rw-0 rw-0 rw-0 address 00h accvie nmiie rw-0 7654 0 321 address 01h btie rw-0 wdtie: watchdog-timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie: oscillator-fault-interrupt enable nmiie: nonmaskable-interrupt enable accvie: flash access violation interrupt enable btie: basic timer1 interrupt enable interrupt flag register 1 and 2 7654 0 ofifg wdtifg 321 rw-0 rw-1 rw-(0) address 02h nmiifg 7654 0 321 address 03h btifg rw-0 wdtifg: set on watchdog-timer overflow (in watchdog mode) or security key violation. reset with v cc power-up, or a reset condition at the rst /nmi pin in reset mode. ofifg: flag set on oscillator fault nmiifg: set via rst /nmi pin btifg: basic timer1 interrupt flag module enable registers 1 and 2 7654 0 321 address 04h/05h rw-0,1: legend: rw: bit can be read and written bit can be read and written. it is reset or set by puc. bit can be read and written. it is reset or set by por. sfr bit not present in device rw-(0,1):
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 10 post office box 655303 ? dallas, texas 75265 memory organization msp430fw423 msp430fw425 msp430fw427 memory interrupt vector code memory size flash flash 8kb 0ffffh ? 0ffe0h 0ffffh ? 0e000h 16kb 0ffffh ? 0ffe0h 0ffffh ? 0c000h 32kb 0ffffh ? 0ffe0h 0ffffh ? 08000h information memory size 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h boot memory size 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h ram size 256 byte 02ffh ? 0200h 512 byte 03ffh ? 0200h 1kb 05ffh ? 0200h peripherals 16-bit 8-bit 8-bit sfr 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the application report features of the msp430 bootstrap loader , literature number slaa089. bsl function pm package pins data transmit 53 - p1.0 data receive 52 - p1.1 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0?n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 11 post office box 655303 ? dallas, texas 75265 flash memory (continued) segment 0 with interrupt vectors segment 1 segment 2 segment n?1 segment n 32kb segment a segment b main memory information memory 0ffffh 0fa00h 0fe00h 0fdffh 0fc00h 0fbffh 0f9ffh 08400h 083ffh 08200h 081ffh 01000h 010ffh 08000h 01080h 0107fh 16kb 0ffffh 0fa00h 0fe00h 0fdffh 0fc00h 0fbffh 0f9ffh 0c400h 0c3ffh 0c200h 0c1ffh 01000h 010ffh 0c000h 01080h 0107fh 8kb 0ffffh 0fa00h 0fe00h 0fdffh 0fc00h 0fbffh 0f9ffh 0e400h 0e3ffh 0e200h 0e1ffh 01000h 010ffh 0e000h 01080h 0107fh peripherals peripherals are connected to the cpu through data, address, and control busses and can be handled using all instructions. for complete module descriptions, refer to the msp430x4xx family user?s guide , literature number slau056. oscillator and system clock the clock system in the msp430xw42x family of devices is supported by the fll+ module that includes support for a 32768-hz watch crystal oscillator, an internal digitally-controlled oscillator (dco) and a high frequency crystal oscillator. the fll+ clock module is designed to meet the requirements of both low system cost and low-power consumption. the fll+ features a digital frequency locked loop (fll) hardware which in conjunction with a digital modulator stabilizes the dco frequency to a programmable multiple of the watch crystal frequency. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the fll+ module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high frequency crystal. main clock (mclk), the system clock used by the cpu. sub-main clock (smclk), the sub-system clock used by the peripheral modules. aclk/n, the buffered output of aclk, aclk/2, aclk/4, or aclk/8.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 12 post office box 655303 ? dallas, texas 75265 brownout, supply voltage supervisor the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. the supply voltage supervisor (svs) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (svm, the device is not automatically reset). the cpu begins code execution after the brownout circuit releases the device reset. however, v cc may not have ramped to v cc(min) at that time. the user must insure the default fll+ settings are not changed until v cc reaches v cc(min) . if desired, the svs circuit can be used to determine when v cc reaches v cc(min) . digital i/o there are six 8-bit i/o ports implemented?ports p1 through p6: all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of ports p1 and p2. read/write access to port-control registers is supported by all instructions. basic timer1 the basic t imer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. both timers can be read and written by software. the basic timer1 can be used to generate periodic interrupts and clock for the lcd module. lcd drive the lcd driver generates the segment and common signals required to drive an lcd display. the lcd controller has dedicated data memory to hold segment drive information. common and segment signals are generated as defined by the mode. static, 2-mux, 3-mux, and 4-mux lcds are supported by this peripheral. watchdog timer the primary function of the watchdog timer (wdt) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_a the primary function of the comparator_a module is to support precision slope analog?to?digital conversions, battery?voltage supervision, and monitoring of external analog signals. scan if the scan interface is used to measure linear or rotational motion and supports lc and resistive sensors such as gmr sensors. the scan if incorporates a v cc /2 generator, a comparator, and a 10-bit dac and supports up to four sensors.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 13 post office box 655303 ? dallas, texas 75265 timer0_a3 timer0_a3 is a 16-bit timer/counter with three capture/compare registers. timer0_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer0_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer0_a3 signal connections input pin number device input signal module input name module block module output signal output pin number 48 - p1.5 ta0clk taclk aclk aclk timer na smclk smclk timer na 48 - p1.5 ta0clk inclk 53 - p1.0 ta0.0 cci0a 53 - p1.0 52 - p1.1 ta0.0 cci0b ccr0 ta0 0 dv ss gnd ccr0 ta0.0 dv cc v cc 51 - p1.2 ta0.1 cci1a 51 - p1.2 caout (internal) cci1b ccr1 ta0 1 dv ss gnd ccr1 ta0.1 dv cc v cc 45 - p2.0 ta0.2 cci2a 45 - p2.0 aclk (internal) cci2b ccr2 ta0 2 dv ss gnd ccr2 ta0.2 dv cc v cc
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 14 post office box 655303 ? dallas, texas 75265 timer1_a5 timer1_a5 is a 16-bit timer/counter with five capture/compare registers. timer1_a5 can support multiple capture/compares, pwm outputs, and interval timing. timer1_a5 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer1_a5 signal connections input pin number device input signal module input name module block module output signal output pin number 32 - p2.5 ta1clk taclk aclk aclk timer na smclk smclk timer na 32 - p2.5 ta1clk inclk 49 - p1.4 ta1.0 cci0a 49 - p1.4 50 - p1.3 ta1.0 cci0b ccr0 ta1 0 dv ss gnd ccr0 ta1.0 dv cc v cc 44 - p2.1 ta1.1 cci1a 44 - p2.1 caout (internal) cci1b ccr1 ta1 1 dv ss gnd ccr1 ta1.1 dv cc v cc 35 - p2.2 ta1.2 cci2a 35 - p2.2 sifo0sig (internal) cci2b ccr2 ta1 2 dv ss gnd ccr2 ta1.2 dv cc v cc 34 - p2.3 ta1.3 cci3a 34 - p2.3 sifo1sig (internal) cci3b ccr3 ta1 3 dv ss gnd ccr3 ta1.3 dv cc v cc 33 - p2.4 ta1.4 cci4a 33 - p2.4 sifo2sig (internal) cci4b ccr4 ta1 4 dv ss gnd ccr4 ta1.4 dv cc v cc
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 15 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access watchdog watchdog timer control wdtctl 0120h timer1_a5 timer1_a interrupt vector ta1iv 011eh _ timer1_a control ta1ctl 0180h capture/compare control 0 ta1cctl0 0182h capture/compare control 1 ta1cctl1 0184h capture/compare control 2 ta1cctl2 0186h capture/compare control 3 ta1cctl3 0188h capture/compare control 4 ta1cctl4 018ah reserved 018ch reserved 018eh timer1_a register ta1r 0190h capture/compare register 0 ta1ccr0 0192h capture/compare register 1 ta1ccr1 0194h capture/compare register 2 ta1ccr2 0196h capture/compare register 3 ta1ccr3 0198h capture/compare register 4 ta1ccr4 019ah reserved 019ch reserved 019eh timer0_a3 timer0_a interrupt vector ta0iv 012eh _ timer0_a control ta0ctl0 0160h capture/compare control 0 ta0cctl0 0162h capture/compare control 1 ta0cctl1 0164h capture/compare control 2 ta0cctl2 0166h reserved 0168h reserved 016ah reserved 016ch reserved 016eh timer0_a register ta0r 0170h capture/compare register 0 ta0ccr0 0172h capture/compare register 1 ta0ccr1 0174h capture/compare register 2 ta0ccr2 0176h reserved 0178h reserved 017ah reserved 017ch reserved 017eh flash flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 16 post office box 655303 ? dallas, texas 75265 peripherals with word access (continued) scan if sif timing state machine 23 siftsm23 01feh : : : sif timing state machine 0 siftsm0 01d0h sif dac register 7 sifdacr7 01ceh : : : sif dac register 0 sifdacr0 01c0h sif control register 5 sifctl5 01beh sif control register 4 sifctl4 01bch sif control register 3 sifctl3 01bah sif control register 2 sifctl2 01b8h sif control register 1 sifctl1 01b6h sif processing state machine vector sifpsmv 01b4h sif counter cnt1/2 sifcnt 01b2h reserved sifdebug 01b0h peripherals with byte access lcd lcd memory 20 lcdm20 0a4h : : : lcd memory 16 lcdm16 0a0h lcd memory 15 lcdm15 09fh : : : lcd memory 1 lcdm1 091h lcd control and mode lcdctl 090h comparator_a comparator_a port disable capd 05bh p _ comparator_a control 2 cactl2 05ah comparator_a control 1 cactl1 059h brownout, svs svs control register svsctl 056h fll+ clock fll+ control 1 fll_ctl1 054h fll+ control 0 fll_ctl0 053h system clock frequency control scfqctl 052h system clock frequency integrator scfi1 051h system clock frequency integrator scfi0 050h basic timer1 bt counter 2 btcnt2 047h bt counter 1 btcnt1 046h bt control btctl 040h
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 17 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access (continued) port p6 port p6 selection p6sel 037h port p6 direction p6dir 036h port p6 output p6out 035h port p6 input p6in 034h port p5 port p5 selection p5sel 033h port p5 direction p5dir 032h port p5 output p5out 031h port p5 input p5in 030h port p4 port p4 selection p4sel 01fh port p4 direction p4dir 01eh port p4 output p4out 01dh port p4 input p4in 01ch port p3 port p3 selection p3sel 01bh port p3 direction p3dir 01ah port p3 output p3out 019h port p3 input p3in 018h port p2 port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt-edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h port p1 port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt-edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special functions sfr module enable 2 me2 005h p sfr module enable 1 me1 004h sfr interrupt flag 2 ifg2 003h sfr interrupt flag 1 ifg1 002h sfr interrupt enable 2 ie2 001h sfr interrupt enable 1 ie1 000h absolute maximum ratings ? voltage applied at v cc to v ss ?0.3 v to + 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (see note) ?0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal . 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (unprogrammed device) ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (programmed device) ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note: all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the tdi/tclk pin when blowing the jtag fuse.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 18 post office box 655303 ? dallas, texas 75265 recommended operating conditions parameter min nom max units supply voltage during program execution (see note 1), v cc (av cc = dv cc = v cc ) msp430xw42x 1.8 3.6 v supply voltage during program execution, svs enabled, poron = 1 (see note 1 and note 2), v cc (av cc = dv cc = v cc ) msp430xw42x 2.0 3.6 v supply voltage during programming flash memory (see note 1), v cc (av cc = dv cc = v cc ) msp430fw42x 2.7 3.6 v supply voltage, v ss (av ss = dv ss = v ss ) 0 0 v operating free-air temperature range, t a msp430xw42x ?40 85 c lfxt1 t l f f lf selected, xts_fll=0 watch crystal 32768 hz lfxt1 crystal frequency, f (lfxt1) (see note 3) xt1 selected, xts_fll=1 ceramic resonator 450 8000 khz ( see n o t e 3) xt1 selected, xts_fll=1 crystal 1000 8000 khz processor frequency (signal mclk) f v cc = 1.8 v dc 4.15 mhz processor frequency (signal mclk), f (system) v cc = 3.6 v dc 8 mhz notes: 1. it is recommended to power av cc and dv cc from the same source. a maximum difference of 0.3 v betweeen av cc and dv cc can be tolerated during power up and operation. 2. the minimum operating supply voltage is defined according to the trip point where por is going active by decreasing supply vo ltage. por is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the svs circuitry. 3. in lf mode, the lfxt1 oscillator requires a watch crystal. in xt1 mode, lfxt1 accepts a ceramic resonator or a crystal. f (mhz) 1.8 v 3.6 v 2.7 v 3 v ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? 4.15 mhz 8 mhz v cc ? supply voltage ? v f (system) ? maximum processor frequency ? mhz supply voltage range during program execution supply voltage range during programming of the flash memory figure 1. maximum frequency vs supply voltage
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 19 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into av cc + dv cc excluding external current, (see note 1) parameter test conditions min nom max unit i active mode, f ( mclk ) = f ( smclk ) = f ( dco ) = 1 mhz, t 40 cto85 c v cc = 2.2 v 200 250 a i (am) f (mclk) = f (smclk) = f (dco) = 1 mhz , f (aclk) = 32,768 hz, xts_fll = 0 (fw42x: program executes in flash) t a = ?40 c to 85 c v cc = 3 v 300 350 a i low-power mode, (lpm0) f ( mclk ) = f ( smclk ) = f ( dco ) = 1 mhz, t 40 cto85 c v cc = 2.2 v 57 70 a i (lpm0) f (mclk) = f (smclk) = f (dco) = 1 mhz , f (aclk) = 32,768 hz, xts_fll = 0 fn_8=fn_4=fn_3=fn_2=0 (see note 3) t a = ?40 c to 85 c v cc = 3 v 92 100 a i low power mode (lpm2) (see note 3) t 40 cto85 c v cc = 2.2 v 11 14 a i (lpm2) low-power mode, (lpm2) (see note 3) t a = ?40 c to 85 c v cc = 3 v 17 22 a t a = ?40 c 0.95 1.4 t a = ?10 c 0.8 1.3 t a = 25 c v cc = 2.2 v 0.7 1.2 t a = 60 c v cc 2.2 v 0.95 1.4 i low-power mode, (lpm3) t a = 85 c 1.6 2.3 a i (lpm3) low power mode , (lpm3) (see note 2 and note 3) t a = ?40 c 1.1 1.7 a () t a = ?10 c 1.0 1.6 t a = 25 c v cc = 3 v 0.9 1.5 t a = 60 c v cc 3 v 1.1 1.7 t a = 85 c 2.0 2.6 t a = ?40 c 0.1 0.5 i ( lpm4 ) low-power mode, (lpm4) (see note 3) t a = 25 c v cc = 2.2 v/3 v 0.1 0.5 a i (lpm4) low power mode, (lpm4) (see note 3) t a = 85 c v cc 2.2 v/3 v 0.8 2.5 a notes: 1. all inputs are tied to 0 v or v cc . outputs do not source or sink any current. the current consumption is measured with active basic timer1 and lcd (aclk selected). the current consumption of the comparator_a and the svs module are specified in the respective sections. 2. the lpm3 currents are characterized with a kds daishinku dt?38 (6 pf) crystal. 3. current for brownout included. current consumption of active mode versus system frequency i (am) = i (am) [1 mhz] f (system) [mhz] current consumption of active mode versus supply voltage i (am) = i (am) [3 v] + 140 a/v (v cc ? 3 v)
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 20 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) schmitt-trigger inputs ? ports p1, p2, p3, p4, p5, and p6; rst /nmi; jtag: tck, tms, tdi/tclk parameter test conditions min typ max unit v positive going input threshold voltage v cc = 2.2 v 1.1 1.5 v v it+ positive-going input threshold voltage v cc = 3 v 1.5 1.9 v v negative going input threshold voltage v cc = 2.2 v 0.4 0.9 v v it? negative-going input threshold voltage v cc = 3 v 0.9 1.3 v v input voltage hysteresis (v v ) v cc = 2.2 v 0.3 1.1 v v hys input voltage hysteresis (v it+ ? v it? ) v cc = 3 v 0.45 1 v inputs px.x, tax.x parameter test conditions v cc min typ max unit p t p1 p2 p1 t p2 e t l t i i l 2.2 v/3 v 1.5 cycle t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signal for the interrupt flag, (see note 1) 2.2 v 62 ns (int) pg for the interrupt flag , (see note 1) 3 v 50 ns t timer a capture timing tax x 2.2 v 62 ns t (cap) timer_a, capture timing tax.x 3 v 50 ns f () timer_a clock frequency taxclk inclk t () =t () 2.2 v 8 mhz f (taext) timer _ a clock frequency externally applied to pin taxclk, inclk t (h) = t (l) 3 v 10 mhz f timer a clock frequency smclk or aclk signal selected 2.2 v 8 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) cycle and time parameters are met. it may be set even with trigger signals shorter than t (int) . both the cycle and timing specifications must be met to ensure the flag is set. t (int) is measured in mclk cycles. leakage current ? ports p1, p2, p3, p4, p5, and p6 (see note 1) parameter test conditions min nom max unit i lkg(px.x) leakage current port px port x: v (px.x) (see note 2) v cc = 2.2 v/3 v 50 na notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the port pin must be selected as an input.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 21 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p3, p4, p5, and p6 parameter test conditions min typ max unit i oh(max) = ?1.5 ma, v cc = 2.2 v, see note 1 v cc ?0.25 v cc v high level output voltage i oh(max) = ?6 ma, v cc = 2.2 v, see note 2 v cc ?0.6 v cc v v oh high-level output voltage i oh(max) = ?1.5 ma, v cc = 3 v, see note 1 v cc ?0.25 v cc v i oh(max) = ?6 ma, v cc = 3 v, see note 2 v cc ?0.6 v cc i ol(max) = 1.5 ma, v cc = 2.2 v, see note 1 v ss v ss +0.25 v low level output voltage i ol(max) = 6 ma, v cc = 2.2 v, see note 2 v ss v ss +0.6 v v ol low-level output voltage i ol(max) = 1.5 ma, v cc = 3 v, see note 1 v ss v ss +0.25 v i ol(max) = 6 ma, v cc = 3 v, see note 2 v ss v ss +0.6 notes: 1. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 12 ma to satisfy the maximum specified voltage drop. 2. the maximum total current, i oh(max) and i ol(max), for all outputs combined, should not exceed 24 ma to satisfy the maximum specified voltage drop. output frequency parameter test conditions min typ max unit f (1 x 60 y 7) c l = 20 pf, v cc = 2.2 v dc 10 mhz f px.y (1 x 6, 0 y 7) c l = 20 pf , i l = 1.5ma v cc = 3 v dc 12 mhz f aclk, f p1.1/ta0.0/mclk, c 20 pf v cc = 2.2 v 8 mhz f mclk, f smclk p1 . 1/ta0 . 0/mclk , p1.5/ta0clk/aclk c l = 20 pf v cc = 3 v 12 mhz p1.5/ta0clk/aclk, f aclk = f lfxt1 = f xt1 40% 60% p1 . 5/ta0clk/aclk , c l = 20 pf f aclk = f lfxt1 = f lf 30% 70% c l 20 pf v cc = 2.2 v / 3 v f aclk = f lfxt1/n 50% t xdc duty cycle of output frequency p1.1/ta0.0/mclk, c 20 pf f mclk = f lfxt1/n 50%? 15 ns 50% 50%+ 15 ns c l = 20 pf, v cc = 2.2 v / 3 v f mclk = f dcoclk 50%? 15 ns 50% 50%+ 15 ns
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 22 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, p3, p4, p5, and p6 (continued) v ol ? low-level output voltage ? v 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p2.4 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c i ol ? typical low-level output current ? ma figure 2 v ol ? low-level output voltage ? v 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p2.4 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c i ol ? typical low-level output current ? ma figure 3 v oh ? high-level output voltage ? v ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p2.4 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c i oh ? typical high-level output current ? ma figure 4 v oh ? high-level output voltage ? v ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p2.4 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c i oh ? typical high-level output current ? ma figure 5 note: one output loaded at a time
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 23 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up lpm3 parameter test conditions min typ max unit f = 1 mhz 6 t d ( lpm3 ) delay time f = 2 mhz v cc = 2.2 v/3 v 6 s t d(lpm3) delay time f = 3 mhz v cc 2.2 v/3 v 6 s ram (see note 1) parameter test conditions min typ max unit vramh cpu halted (see note 1) 1.6 v notes: 1. this parameter defines the minimum supply voltage when the data in the program memory ram remain unchanged. no program execution should take place during this supply voltage condition. lcd parameter test conditions min typ max unit v (33) voltage at p5.7/r33 2.5 v cc +0.2 v (23) analog voltage voltage at p5.6/r23 v 3v (v 33 ?v 03 ) 2/3 + v 03 v v (13) analog voltage voltage at p5.5/r13 v cc = 3 v (v (33) ?v (03) ) 1/3 + v (03) v v (33) ? v (03) voltage at r33/r03 2.5 v cc +0.2 i (r03) r03 = v ss no load at all 20 i (r13) input leakage p5.5/r13 = v cc /3 segment and common lines 20 na i (r23) pg p5.6/r23 = 2 v cc /3 common li nes, v cc = 3 v 20 v (sxx0) v (03) v (03) ? 0.1 v (sxx1) se g ment line i 3 a v 3v v (13) v (13) ? 0.1 v v (sxx2) segment line voltage i (sxx) = ?3 a, v cc = 3 v v( 23) v (23) ? 0.1 v v (sxx3) v( 33) v (33) + 0.1
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 24 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) comparator_a (see note 1) parameter test conditions min typ max unit i caon 1 carsel 0 caref 0 v cc = 2.2 v 25 40 a i (cc) caon = 1, carsel = 0, caref = 0 v cc = 3 v 45 60 a i caon = 1, carsel = 0, caref 1/2/3 v cc = 2.2 v 30 50 a i (refladder/refdiode) caref = 1/2/3, no load at p1.6/ca0 and p1.7/ca1 v cc = 3 v 45 71 a v (ref025) voltage @ 0.25 v cc node v cc pca0 = 1, carsel = 1, caref = 1, no load at p1.6/ca0 and p1.7/ca1 v cc = 2.2 v / 3 v 0.23 0.24 0.25 v (ref050) voltage @ 0.5 v cc node v cc pca0 = 1, carsel = 1, caref = 2, no load at p1.6/ca0 and p1.7/ca1 v cc = 2.2v / 3 v 0.47 0.48 0.50 v (see fi g ure 6 and pca0 = 1, carsel = 1, caref = 3, no load at p1 6/ca0 and p1 7/ca1; v cc = 2.2 v 390 480 540 mv v (refvt) (see figure 6 and figure 7) no load at p1.6/ca0 and p1.7/ca1; t a = 85 c v cc = 3.0 v 400 490 550 mv v (ic) common-mode input voltage range caon = 1 v cc = 2. 2v/3 v 0 v cc ?1.0 v v (offset) offset voltage see note 2 vcc = 2.2 v/3 v ?30 30 mv v hys input hysteresis caon = 1 v cc = 2.2 v / 3 v 0 0.7 1.4 mv t a = 25 c, v cc = 2.2 v 130 210 300 ns t t a = 25 c , overdrive 10 mv, without filter: caf = 0 v cc = 3 v 80 150 240 ns t (response lh) t a = 25 c v cc = 2.2 v 1.4 1.9 3.4 s t a = 25 c overdrive 10 mv, with filter: caf = 1 v cc = 3 v 0.9 1.5 2.6 s t a = 25 c v cc = 2.2 v 130 210 300 ns t t a = 25 c overdrive 10 mv, without filter: caf = 0 v cc = 3 v 80 150 240 ns t (response hl) t a = 25 c, v cc = 2.2 v 1.4 1.9 3.4 s t a = 25 c , overdrive 10 mv, with filter: caf = 1 v cc = 3.0 v 0.9 1.5 2.6 s notes: 1. the leakage current for the comparator_a terminals is identical to i lkg(px.x) specification. 2. the input offset voltage can be cancelled by using the caex bit to invert the comparator_a inputs on successive measurements. the two successive measurements are then summed together.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 25 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 3 v typical v (refvt) ? reference voltage ? mv reference voltage vs free-air temperature figure 6 t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 2.2 v typical v (refvt) ? reference voltage ? mv reference voltage vs free-air temperature figure 7 _ + caon 0 1 v+ 0 1 caf low pass filter 2 s to internal modules set caifg flag caout v? v cc 1 0 v 0 figure 8. block diagram of comparator_a module overdrive v caout t (response) v+ v? 400 mv figure 9. overdrive definition
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 26 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) por brownout, reset (see notes 1 and 2) parameter test conditions min typ max unit t d(bor) 2000 s v cc(start) dv cc /dt 3 v/s (see figure 10) 0.7 v (b_it?) v v (b_it?) brownout dv cc /dt 3 v/s (see figure 10, figure 11, figure 12) 1.71 v v hys(b_it?) b rownout dv cc /dt 3 v/s (see figure 10) 70 130 180 mv t (reset) pulse length needed at rst /nmi pin to accepted reset internally, v cc = 2.2 v/3 v 2 s notes: 1. the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it?) + v hys(b_it?) is 1.8 v. 2. during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it?) + v hys(b_it?) . the default fll+ settings must not be changed until v cc v cc(min) , where v cc(min) is the minimum supply voltage for the desired operating frequency. see the msp430x4xx family user?s guide (slau056) for more information on the brownout/svs circuit. 0 1 v v cc(start) v hys(b_it?) v cc t d(bor) (b_it?) figure 10. por/brownout reset (bor) vs supply voltage v cc (drop) ? v 0 0.5 1 1.5 2 0.001 1 1000 v = 3 v typical conditions 1 ns 1 ns t pw ? pulse width ? st pw ? pulse width ? s cc v cc 3 v v cc(drop) t pw figure 11. v cc(drop) level with a square voltage drop to generate a por/brownout signal
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 27 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) v cc 3 v v cc(drop) t pw 0 0.5 1 1.5 2 t pw ? pulse width ? s 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r v = 3 v typical conditions cc v cc (drop) ? v figure 12. v cc(drop) level with a triangle voltage drop to generate a por/brownout signal svs (supply voltage supervisor/monitor) (see notes 1 and 2) parameter test conditions min nom max unit t dv cc /dt > 30 v/ms (see figure 13) 5 150 s t d(svsr) dv cc /dt 30 v/ms 2000 s t d(svson) svson, switch from vld=0 to vld 0, v cc = 3 v 20 150 s t settle vld 0 ? 12 s v (svsstart) vld 0, v cc /dt 3 v/s (see figure 13) 1.55 1.7 v vld = 1 70 120 155 mv v h y s ( svs_it? ) v cc /dt 3 v/s (see figure 13) vld = 2 .. 14 v (svs_it?) x 0.004 v (svs_it?) x 0.008 v hys(svs _ it ? ) v cc /dt 3 v/s (see figure 13), external voltage applied on svsin vld = 15 4.4 10.4 mv vld = 1 1.8 1.9 2.05 vld = 2 1.94 2.1 2.25 vld = 3 2.05 2.2 2.37 vld = 4 2.14 2.3 2.48 vld = 5 2.24 2.4 2.6 vld = 6 2.33 2.5 2.71 v /dt 3 v/s (see figure 13) vld = 7 2.46 2.65 2.86 v (svs it ) v cc /dt 3 v/s (see figure 13) vld = 8 2.58 2.8 3 v v (svs_it?) vld = 9 2.69 2.9 3.13 v vld = 10 2.83 3.05 3.29 vld = 11 2.94 3.2 3.42 vld = 12 3.11 3.35 3.61 ? vld = 13 3.24 3.5 3.76 ? vld = 14 3.43 3.7 ? 3.99 ? v cc /dt 3 v/s (see figure 13), external voltage applied on svsin vld = 15 1.1 1.2 1.3 i cc(svs) (see note 1) vld 0, v cc = 2.2 v/3 v 10 15 a ? the recommended operating voltage range is limited to 3.6 v. ? t settle is the settling time that the comparator o/p needs to have a stable level after vld is switched vld 0 to a different vld value somewhere between 2 and 15. the overdrive is assumed to be > 50 mv. notes: 1. the current consumption of the svs module is not included in the i cc current consumption data. 2. the svs is not active at power up.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 28 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) v cc(start) v cc v (b_it?) brownout region v (svsstart) v software sets vld>0:svs is active undefined 0 1 brownout 0 1 0 1 set por brownout region svs circuit is active from vld > to v cc < v (b_it?) svs out v hys(svs_it?) v hys(b_it?) t d(bor) t d(svson) t d(svsr) t d(bor) (svs_it?) figure 13. svs reset (svsr) vs supply voltage v cc(drop) 0 0.5 1 1.5 2 1 ns 1 ns t pw ? pulse width ? s 1 10 1000 t f t r t ? pulse width ? s 100 t f = t r rectangular drop v cc(drop) ? v triangular drop 3 v v cc t pw 3 v v cc t pw v cc(drop) figure 14. v cc(drop) with a square voltage drop and a triangle voltage drop to generate an svs signal
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 29 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) dco parameter test conditions v cc min typ max unit f (dcoclk) n (dco) =01eh, fn_8=fn_4=fn_3=fn_2=0, d = 2, dcoplus= 0, f crystal = 32.738 khz 2.2 v/3 v 1 mhz f fn 8 fn 4 fn 3 fn 2 0 dcoplus 1 2.2 v 0.3 0.65 1.25 mhz f (dco=2) fn_8=fn_4=fn_3=fn_2=0 , dcoplus = 1 3 v 0.3 0.7 1.3 mhz f fn 8 fn 4 fn 3 fn 2 0 dcoplus 1 2.2 v 2.5 5.6 10.5 mhz f (dco=27) fn_8=fn_4=fn_3=fn_2=0, dcoplus = 1 3 v 2.7 6.1 11.3 mhz f fn 8 fn 4 fn 3 0 fn 2 1; dcoplus 1 2.2 v 0.7 1.3 2.3 mhz f (dco=2) fn_8=fn_4=fn_3=0, fn_2=1; dcoplus = 1 3 v 0.8 1.5 2.5 mhz f fn 8 fn 4 fn 3 0 fn 2 1; dcoplus 1 2.2 v 5.7 10.8 18 mhz f (dco=27) fn_8=fn_4=fn_3=0, fn_2=1; dcoplus = 1 3 v 6.5 12.1 20 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x; dcoplus 1 2.2 v 1.2 2 3 mhz f (dco=2) fn_8=fn_4=0, fn_3= 1, fn_2=x; dcoplus = 1 3 v 1.3 2.2 3.5 mhz f fn 8 fn 4 0 fn 3 1 fn 2 x; dcoplus 1 2.2 v 9 15.5 25 mhz f (dco=27) fn_8=fn_4=0, fn_3= 1, fn_2=x;, dcoplus = 1 3 v 10.3 17.9 28.5 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x; dcoplus 1 2.2 v 1.8 2.8 4.2 mhz f (dco=2) fn_8=0, fn_4= 1, fn_3= fn_2=x; dcoplus = 1 3 v 2.1 3.4 5.2 mhz f fn 8 0 fn 4 1 fn 3 fn 2 x; dcoplus 1 2.2 v 13.5 21.5 33 mhz f (dco=27) fn_8=0, fn_4=1, fn_3= fn_2=x; dcoplus = 1 3 v 16 26.6 41 mhz f fn 8 1 fn 4 fn 3 fn 2 x; dcoplus 1 2.2 v 2.8 4.2 6.2 mhz f (dco=2) fn_8=1, fn_4=fn_3=fn_2=x; dcoplus = 1 3 v 4.2 6.3 9.2 mhz f fn 8 1 fn 4 fn 3 fn 2 x dcoplus 1 2.2 v 21 32 46 mhz f (dco=27) fn_8=1,fn_4=fn_3=fn_2=x,dcoplus = 1 3 v 30 46 70 mhz s step size between adjacent dco taps: 1 < tap 20 1.06 1.11 s n step size between adjacent dco taps: s n = f dco(tap n+1) / f dco(tap n) (see figure 16 for taps 21 to 27) tap = 27 1.07 1.17 d temperature drift, n ( d co) = 01eh, fn_8=fn_4=fn_3=fn_2=0 2.2 v ?0.2 ?0.3 ?0.4 % / c d t temperature drift , n (dco) = 01eh , fn _ 8=fn _ 4=fn _ 3=fn _ 2=0 d = 2, dcoplus = 0 3 v ?0.2 ?0.3 ?0.4 % / c d v drift with v cc variation, n (dco) = 01eh, fn_8=fn_4=fn_3=fn_2=0 d = 2, dcoplus = 0 2.2 v/3 v 0 5 15 %/v t a ? c v cc ? v f (dco) f (dco20 c) f (dco) f (dco3v) 1.8 3.0 2.4 3.6 1.0 20 60 40 85 1.0 0 ?20 ?40 0 figure 15. dco frequency vs supply voltage v cc and vs ambient temperature
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 30 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? 127 20 1.11 1.17 dco tap s n - stepsize ratio between dco taps min max 1.07 1.06 figure 16. dco tap step size dco frequency adjusted by bits 2 9 to 2 5 in scfi1 {n {dco} } fn_2=0 fn_3=0 fn_4=0 fn_8=0 fn_2=1 fn_3=0 fn_4=0 fn_8=0 fn_2=x fn_3=1 fn_4=0 fn_8=0 fn_2=x fn_3=x fn_4=1 fn_8=0 fn_2=x fn_3=x fn_4=x fn_8=1 legend tolerance at tap 27 tolerance at tap 2 overlapping dco ranges: uninterrupted frequency range f (dco) figure 17. five overlapping dco ranges controlled by fn_x bits
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 31 post office box 655303 ? dallas, texas 75265 crystal oscillator, lfxt1 oscillator (see notes 1 and 2) parameter test conditions v cc min typ max unit osccapx = 0h 2.2 v/3 v 0 c integrated load capacitance osccapx = 1h 2.2 v/3 v 10 pf c xin integrated load capacitance osccapx = 2h 2.2 v/3 v 14 pf osccapx = 3h 2.2 v/3 v 18 osccapx = 0h 2.2 v/3 v 0 c integrated load capacitance osccapx = 1h 2.2 v/3 v 10 pf c xout integrated load capacitance osccapx = 2h 2.2 v/3 v 14 pf osccapx = 3h 2.2 v/3 v 18 v il input levels at xin see note 3 2 2 v/3 v v ss 0.2 v cc v v ih input levels at xin see note 3 2.2 v/3 v 0.8 v cc v cc v notes: 1. the parasitic capacitance from the package and board may be estimated to be 2pf. the effective load capacitor for the c rystal is (c xin x c xout ) / (c xin + c xout ). it is independent of xts_fll. 2. to improve emi on the low-power lfxt1 oscillator, particularly in the lf mode (32 khz), the following guidelines must be observe: ? keep as short a trace as possible between the ?xw42x and the crystal. ? design a good ground plane around oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ? avoid running pcb traces underneath or adjacent to xin an xout pins. ? use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ? if conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. ? do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. 3. applies only when using an external logic-level clock source. xts_fll must be set. not applicable when using a crystal or resonator. 4. external capacitance is recommended for precision real-time clock applications; osccapx = 0h.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 32 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) scan if, port drive, port timing parameter test conditions v cc min typ max unit v ol(sifchx) voltage drop due to excitation transistor?s on?resistance. (see figure 18) i (sifchx) = 2.0 ma, siften = 1 3 v 0.3 v v oh(sifchx) (see note 1) voltage drop due to damping transistor?s on?resistance. (see figure 18) i (sifchx) = ?200 a, siften = 1 3 v 0.1 v v ol(sifcom) i (sifcom) = 3 ma, sifsh = 1 2.2 v/3 v 0 0.1 v i sifchx(tri-state) v (sifchx) = 0 v to av cc , port function disabled, sifsh = 1 3 v ?50 50 na t dsifch : t wex(tsm) ?t wsifch (see figure 18) change of pulse width of internal signal sifex(tsm) to pulse width at pin sifchx i (sifchx) = 3 ma, t ex(sifchx) = 500 ns 20% 2.2 v/3 v ?20 20 ns note: 1. sifcom=1.5v , supplied externally. (see figure 19). t ex(sifchx) sifex(tsm) p6.x/sifch.x t sifch(x) figure 18. p6.x/sifchx timing, sifchx function selected i (sifchx) p6.x/sifch.x sifcom v ol(sifchx) v oh(sifchx) damping transistor excitation transistor figure 19. voltage drop due to on-resistance
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 33 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) scan if, sample capacitor/ri timing parameter test conditions v cc min typ max unit c shc(sifchx) sample capacitance at sifchx pin sifex(tsm) = 1, sifsh = 1 2.2 v/3 v 5 7 pf ri (sifchx) serial input resistance at the sifchx pin sifex(tsm) = 1, sifsh = 1 2.2 v/3 v 1.5 3 k t hold (see note 1) maximum hold time v sample < 3 mv 62 s notes: 1. the sampled voltage at the sample capacitance varies less than 3 mv ( v sample ) during the hold time t hold. if the voltage is sampled after t hold , the sampled voltage may be any other value. 2. the minimum sampling time (7.6 x tau for 1/2 lsb accuracy) with maximum c shc(sifchx) and ri (sifchx) and ri (source) is t sample(min) ~ 7.6 x c shc(sifchx) x (ri (sifchx) + ri (source) ) with ri (source) estimated at 3 k , t sample(min) = 319 ns. scan if, v cc /2 generator parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc (connected together) av ss = dv ss (connected together) 2.2 3.6 v ai scan if v cc /2 g enerator o p eratin g c l at sifcom p in = 470 nf 20%, 2.2 v 250 350 na ai cc generator operating supply current into av cc terminal c l at sifcom pin = 470 nf 20% , f refresh(sifcom) =32768 hz 3 v 370 450 na f refresh(sifcom) v cc /2 refresh frequency source clock = aclk 2.2 v/3 v 30 32.768 khz v (sifcom) output voltage at pin sifcom c l at sifcom pin = 470 nf 20%, i_load = 1 a av cc /2 ? .05 av cc /2 av cc /2 + .05 v i sifcom source current (see note 2 2.2 v ?500 a i source(sifcom) current (see note 2 and figure 20) 3 v ?900 a i sifcom sink current (see note 2 2.2 v 150 na i sink(sifcom) current (see note 2 and figure 20) 3 v 180 na t time to recover from voltage drop i load1 = i load3 = 0 ma i 3ma t 500ns 2 2 v/3 v 30 s t recovery(sifcom) from voltage drop on load i load2 = 3 ma, t load(on) = 500ns, c l at sifcom pin = 470 nf 20% 2.2 v/3 v 30 s t on(sifcom) time to reach 98% after v cc/ 2 is switched on c l at sifcom pin = 470 nf 20% f refresh(sifcom) = 32768 hz 2.2 v/3 v 1.7 6 ms t vccsettle(sifcom) (see note 1) settling time to v cc /512 (2 lsb) after av voltage sifen =1, sifvcc2 =1, sifsh =0, av cc = av cc ?100 mv f refresh(sifcom) = 32768 hz 2.2 v/3 v 80 ms (see note 1) after av cc voltage change av cc = av cc + 100mv f refresh(sifcom) = 32768 hz 2.2 v/3 v 3 ms notes: 1. the settling time after an av cc voltage change is the time to for the voltage at pin sifcom to settle to av cc /2 2lsb. 2. the sink and source currents are a function of the voltage at the pin sifcom. the maximum currents are reached if sifcom is shorted to gnd or v cc . due to the topology of the output section (refer to figure 20) the v cc /2 generator can source relatively large currents but can sink only small currents.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 34 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) i source(sifcom) sifcom v cc v cc /2 i sink(sifcom) figure 20. p6.x/sifchx timing, sifchx function selected scan if, 10-bit dac (see note 1) parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc (connected together) av ss = dv ss (connected together) 2.2 3.6 v ai scan if 10-bit dac o p eratin g su pp l y c l at sifcom pin = 470 nf 20%, 2.2 v 23 45 a ai cc operating supply current into av cc terminal c l at sifcom pin = 470 nf 20% , f refresh(sifcom) = 32768 hz 3 v 33 60 a resolution 10 bit inl r l = 1000 m , c l = 20 pf 2.2 v/3 v 2 5 lsb dnl r l = 1000 m , c l = 20 pf 2.2 v/3 v 1 lsb e zs zero scale error 2.2 v/3 v 10 mv e g gain error 2.2 v/3 v 0.6 % r o output resistance 25 50 k t on(sifdac) on time after av cc of sifdac is switched on v +sifca ? v sifdac = 6 mv 2.2 v/3 v 2.0 s t settling time sifdac code = 1c0h 240h v sifdac(240h) ? v +sifca = +6 mv 2.2 v/3 v 2.0 s t settle(sifdac) settling time sifdac code = 240h 1c0h, v sifdac(1c0h) ? v +sifca = ?6 mv 2.2 v/3 v 2.0 s notes: 1. the sifdac operates from av cc and sifv ss . all parameters are based on these references.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 35 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) scan if, comparator parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc (connected together) av ss = dv ss (connected together) 2.2 3.6 v ai scan if comparator operating supply current 2.2 v 25 35 a ai cc operating supply current into av cc terminal 3 v 35 50 a v ic common mode input voltage range (see note 1) 2.2 v/3 v 0.9 av cc ? 0.5 v v offset input offset voltage 2.2 v/3 v 30 mv dv offset /dt temperature coefficient of v offset 2.2 v/3 v 10 v/ c dv offset /dv cc v offset supply voltage (v cc ) sensitivity 2.2 v/3 v 0.3 mv/v v input voltage hysteresis v v 05xv 2.2v 0 5.0 mv v hys input voltage hysteresis v +terminal = v ?terminal = 0.5 x v cc 3.0v 0 6.0 mv t on(sifca) on time after sifca is switched on v +sifca ? v sifdac = +6 mv v +sifca = 0.5 x av cc 2.2 v/3 v 2.0 us t settle(sifca) settle time v +sifca ? v sifdac= ?12 mv 6 mv v +sifca = 0.5 x av cc 2.2 v/3 v 2.0 us notes: 1. the comparator output is reliable when at least one of the input signals is within the common mode input voltage range. scan if, sifclk oscillator parameter test conditions v cc min typ max unit av cc analog supply voltage av cc = dv cc (connected together) av ss = dv ss (connected together) 2.2 3.6 v ai scan if oscillator operating supply current 2.2 v 75 a ai cc operating supply current into av cc terminal 3 v 90 a f 0 scan if oscillator at t 25oc sifclkfq 0000 sifnom = 0 1.8 3.2 f sifclkg = 0 scan if oscillator at minimum setting t a =25oc, sifclkfq=0000 sifnom = 1 0.45 0.8 f 8 scan if oscillator at t 25oc sifclkfq 0000 sifnom = 0 4 mhz f sifclkg = 8 scan if oscillator at nominal setting t a =25oc, sifclkfq=0000 sifnom = 1 1 mhz f 15 scan if oscillator at t 25oc sifclkfq 0000 sifnom = 0 4.48 6.8 f sifclkg = 15 scan if oscillator at maximum setting t a =25oc, sifclkfq=0000 sifnom = 1 1.12 1.7 t on(sifclkg) settling time to full operation after v cc is switched on 2.2 v/3 v 150 500 ns s (sifclk) frequency change per 1 sifclkfq (sifctl5) step s (sifclk) = f (sifclkfq + 1) / f (sifclkfq) 2.2 v/3 v 1.01 1.05 1.18 hz/hz d t temperature coefficient sifclkfq (sifctl5) = 8 2.2 v/3 v 0.35 % / c d v frequency vs. supply voltage v cc variation sifclkfq (sifctl5) = 8 2.2 v/3 v 2 %/v
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 36 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory parameter test conditions v cc min nom max unit v cc(pgm/ erase) program and erase supply voltage 2.7 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from dv cc during program 2.7 v/ 3.6 v 3 5 ma i erase supply current from dv cc during erase 2.7 v/ 3.6 v 3 7 ma t cpt cumulative program time see note 1 2.7 v/ 3.6 v 10 ms t cmerase cumulative mass erase time see note 2 2.7 v/ 3.6 v 200 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time 35 t block, 0 block program time for 1 st byte or word 30 t block, 1-63 block program time for each additional byte or word see note 3 21 t t block, end block program end-sequence wait time see note 3 6 t ftg t mass erase mass erase time 5297 t seg erase segment erase time 4819 notes: 1. the cum ulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. 2. the mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/f ftg ,max = 5297x1/476khz). to achieve the required cumulative mass erase time the flash controller?s mass erase operation can be repeated until this time is met. (a worst case minimum of 19 cycles are required). 3. these values are hardwired into the flash controller?s state machine (t ftg = 1/f ftg ). jtag interface parameter test conditions v cc min nom max unit f tck input frequency see note 1 2.2 v 0 5 mhz f tck tck input frequency see note 1 3 v 0 10 mhz r internal internal pull-up resistance on tms, tck, tdi/tclk see note 2 2.2 v/ 3 v 25 60 90 k notes: 1. f tck may be restricted to meet the timing requirements of the module selected. 2. tms, tdi/tclk, and tck pull-up resistors are implemented in all versions. jtag fuse (see note 1) parameter test conditions v cc min nom max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on tdi/tclk for fuse-blow 6 7 v i fb supply current into tdi/tclk during fuse blow 100 ma t fb time to blow fuse 1 ms notes: 1. once the fuse is blown, no further access to the msp430 jt ag/t est and emulation features is possible. the jtag block is switched to bypass mode.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 37 post office box 655303 ? dallas, texas 75265 application information input/output schematic port p1, p1.0 to p1.5, input/output with schmitt-trigger t0aclk ? p1out.x module x out p1dir.x direction control from module p1sel.x d en interrupt edge select p1ies.x p1sel.x p1ie.x p1ifg.x p1irq.x en set q 0 1 1 0 pad logic 0: input 1: output bus keeper capd.x pnsel.x pndir.x direction from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in p1sel.1 p1dir.1 p1out.1 p1in.1 p1ie.1 p1ifg.1 p1ies.1 p1sel.2 p1dir.2 p1out.2 p1in.2 p1ie.2 p1ifg.2 p1ies.2 p1sel.3 p1dir.3 p1out.3 p1in.3 p1ie.3 p1ifg.3 p1ies.3 p1sel.4 p1dir.4 p1out.4 p1in.4 p1ie.4 p1ifg.4 p1ies.4 p1sel.5 p1dir.5 p1out.5 p1in.5 p1ie.5 p1ifg.5 p1ies.5 p1sel.0 p1dir.0 p1out.0 p1in.0 p1ie.0 p1ifg.0 p1ies.0 svsout p1dir.1 p1dir.2 p1dir.3 p1dir.4 p1dir.5 p1dir.0 aclk mclk module x in p1in.x p1.5/ta0clk/aclk p1.0/ta0.0 p1.1/ta0.0/mclk p1.2/ta0.1 p1.4/ta1.0 p1.3/ta1.0/svsout control note: 0 x 5. port function is active if capd.x = 0 ? timer0_a ? timer1_a out0 sig. ? out1 sig. ? cci0a ? cci1a ? cci0b ? cci0b? cci0a? out0 sig. ?
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 38 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p1, p1.6, p1.7 input/output with schmitt-trigger comparator_a p1out.7 dvss p1dir.7 p1sel.7 d en interrupt edge select p1ies.7 p1sel.7 p1ie.7 p1ifg.7 p1irq.07 en set q 0 1 1 0 capd.7 p1out.6 dvss p1dir.6 p1sel.6 d en interrupt edge select p1ies.x p1sel.x p1ifg.7 p1irq.07 p1.6/ ca0 en set q 0 1 1 0 capd.6 note: port function is active if capd.6 = 0 p1in.6 unused p1.7/ ca1 reference block cci1b caf caref p2ca caex caref to timer_ax ? + 2 avcc ca0 ca1 pad logic 0: input 1: output bus keeper pad logic 0: input 1: output bus keeper p1dir.6 p1dir.7 p1in.7 unused p1ie.7 note: port function is active if capd.7 = 0
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 39 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p2, p2.0 to p2.7, input/output with schmitt-trigger p2sel.1 p2dir.1 p2out.1 p2in.1 p2ie.1 p2ifg.1 p2ies.1 p2sel.2 p2dir.2 p2out.2 p2in.2 p2ie.2 p2ifg.2 p2ies.2 p2sel.3 p2dir.3 p2out.3 p2in.3 p2ie.3 p2ifg.3 p2ies.3 p2sel.4 p2dir.4 p2out.4 p2in.4 p2ie.4 p2ifg.4 p2ies.4 p2sel.5 p2dir.5 p2out.5 p2in.5 p2ie.5 p2ifg.5 p2ies.5 p2sel.0 p2dir.0 p2out.0 p2in.0 p2ie.0 p2ifg.0 p2ies.0 p2dir.1 p2dir.2 p2dir.0 0: port active 1: segment xx p2sel.6 p2dir.6 p2sel.7 p2dir.7 p2dir.6 p2dir.7 p2out.6 p2out.7 p2in.6 p2in.7 caout p2ie.6 p2ie.7 p2ifg.6 p2ifg.7 p2ies.6 p2ies.7 p2dir.3 p2dir.4 p2dir.5 p2out.x module x out p2dir.x direction control from module p2sel.x d en interrupt edge select p2ies.x p2sel.x p2ie.x p2ifg.x p2irq.x p2.x en set q 0 1 1 0 pad logic 0: input 1: output bus keeper pnsel.x pndir.x direction from module pnout.x module x out pnin.x pnie.x pnifg.x pnies.x module x in module x in p2in.x control note: 0 x 7 ? timer0_a ? timer1_a scan if out2 sig. ? cci2a ? dvss unused unused p2.7/sifclkg/s18 p2.6/caout/s19 p2.5/ta1clk/s20 p2.0/ta0.2 p2.1/ta1.1 p2.2/ta1.2/s23 p2.4/ta1.4/s21 p2.3/ta1.3/s22 segment xx function active lcdm.5 lcdm.6 lcdm.7 p2.2 to p2.5 p2.0, p2.1 p2.6, p2.7 out1 sig.? out2 sig.? out3 sig.? out4 sig.? cci1a ? cci2a ? cci3a ? cci4a ? ta1clk1 ? sifclkg
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 40 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p3, p3.0 to p3.7, input/output with schmitt-trigger p3sel.0 p3dir.0 p3out.0 p3in.0 0: port active 1: segment xx dvss unused p3out.x module x out p3dir.x direction control from module p3sel.x d en p3.x 0 1 1 0 pad logic 0: input 1: output bus keeper pnsel.x pndir.x direction from module pnout.x module x out pnin.x module x in module x in p3in.x control note: 0 x 7 dvss dvss dvss dvss dvss unused unused unused unused unused unused segment xx function active lcdm.6 p3.2 to p3.7 p3.0, p3.1 p3.7/s10 p3.6/s11 p3.5/s12 p3.0/s17 p3.1/s16 p3.2/s15 p3.4/s13 p3.3/s14 lcdm.7 lcdm.5 unused dvss dvss p3sel.1 p3dir.1 p3out.1 p3in.1 p3sel.2 p3dir.2 p3out.2 p3in.2 p3sel.3 p3dir.3 p3out.3 p3in.3 p3sel.4 p3dir.4 p3out.4 p3in.4 p3sel.5 p3dir.5 p3out.5 p3in.5 p3sel.6 p3dir.6 p3out.6 p3in.6 p3sel.7 p3dir.7 p3out.7 p3in.7 p3dir.0 p3dir.1 p3dir.2 p3dir.3 p3dir.4 p3dir.5 p3dir.6 p3dir.7
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 41 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p4, p4.0 to p4.7, input/output with schmitt-trigger p4sel.0 p4dir.0 p4out.0 p4in.0 0: port active 1: segment xx dvss unused p4out.x module x out p4dir.x direction control from module p4sel.x d en p4.x 0 1 1 0 pad logic 0: input 1: output bus keeper pnsel.x pndir.x direction from module pnout.x module x out pnin.x module x in module x in p4in.x control note: 0 x 7 dvss dvss dvss dvss dvss unused unused unused unused unused unused segment xx function active lcdm.6 lcdm.7 lcdm.5 unused dvss dvss p4.7/s2 p4.6/s3 p4.5/s4 p4.0/s9 p4.1/s8 p4.2/s7 p4.4/s5 p4.3/s6 p4sel.1 p4dir.1 p4out.1 p4in.1 p4sel.2 p4dir.2 p4out.2 p4in.2 p4sel.3 p4dir.3 p4out.3 p4in.3 p4sel.4 p4dir.4 p4out.4 p4in.4 p4sel.5 p4dir.5 p4out.5 p4in.5 p4sel.6 p4dir.6 p4out.6 p4in.6 p4sel.7 p4dir.7 p4out.7 p4in.7 p4dir.0 p4dir.1 p4dir.2 p4dir.3 p4dir.4 p4dir.5 p4dir.6 p4dir.7
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 42 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p5, p5.0, p5.1, input/output with schmitt-trigger p5sel.0 p5dir.0 p5out.0 p5in.0 s1 p5dir.0 dvss unused pnsel.x pndir.x direction from module pnout.x module x out pnin.x segment module x in control note: x = 0, 1 0: port active 1: segment p5out.x module x out p5dir.x direction control from module p5sel.x d en p5.x 0 1 1 0 pad logic 0: input 1: output bus keeper module x in p5in.x segment xx or function active lcdm.6 lcdm.7 lcdm.5 p5.0/s1 p5.1/s0 comx or rxx dvss unused p5sel.1 p5dir.1 p5out.1 p5in.1 s0 p5dir.1 dvss unused
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 43 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p5, p5.2 to p5.4, input/output with schmitt-trigger p5sel.2 p5dir.2 p5out.2 p5in.2 com1 p5dir.2 dvss unused pnsel.x pndir.x direction from module pnout.x module x out pnin.x comx module x in control note: 2 x 4 dvss unused 0: port active 1: comx function p5out.x module x out p5dir.x direction control from module p5sel.x d en p5.x 0 1 1 0 pad logic 0: input 1: output bus keeper module x in p5in.x comx active p5.2/com1 p5.3/com2 dvss unused p5sel.3 p5dir.3 p5out.3 p5in.3 com2 p5dir.3 dvss unused p5sel.4 p5dir.4 p5out.4 p5in.4 com3 p5dir.4 dvss unused p5.4/com3 note: the direction control bits p5sel.2, p5sel.3, and p5sel.4 are used to distinguish between port and common functions. note that a 4mux lcd requires all common signals com3 to com0, a 3mux lcd requires com2 to com0, 2mux lcd requires com1 to com0, and a static lcd requires only com0.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 44 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p5, p5.5 to p5.7, input/output with schmitt-trigger p5sel.5 p5dir.5 p5out.5 p5in.5 r13 p5dir.5 dvss unused pnsel.x pndir.x direction from module pnout.x module x out pnin.x rxx module x in control note: 5 x 7 dvss unused 0: port active 1: rxx function p5out.x module x out p5dir.x direction control from module p5sel.x d en p5.x 0 1 1 0 pad logic 0: input 1: output bus keeper module x in p5in.x rxx active p5.5/r13 p5.6/r23 dvss unused p5sel.6 p5dir.6 p5out.6 p5in.6 r23 p5dir.6 dvss unused p5sel.7 p5dir.7 p5out.7 p5in.7 r33 p5dir.7 dvss unused p5.7/r33 note: the direction control bits p5sel.5, p5sel.6, and p5sel.7 are used to distinguish between port and lcd analog level functions. note that 4mux and 3mux lcds require all rxx signals r33 to r03, a 2mux lcd requires r33, r13, and r03, and a static lcd requires only r33 and r03.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 45 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p6, p6.0, p6.1, p6.2, p6.4, p6.5, input/output with schmitt-trigger p6in.x module x in pad logic en d p6out.x p6dir.x p6sel.x module x out direction control from module 0 1 0 1 bus keeper to/from scan i/f 0: input 1: output x: bit identifier = 0, 1, 2, 4, or 5 p6.0/sifch0 p6.1/sifch1 p6.2/sifch2 p6.4/sifci0 p6.5/sifci1 p6.x p6sel.x must be set if the corresponding pins are used by the scan if. note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, if an analog signal is applied to the pin. pnsel.x pndir.x dir. control from module pnout.x module x out pnin.x module x in p6sel.0 p6dir.0 p6dir.0 p6out.0 dv ss p6in.0 unused p6sel.1 p6dir.1 p6dir.1 p6out.1 dv ss p6in.1 unused p6sel.2 p6dir.2 p6dir.2 p6out.2 dv ss p6in.2 unused p6sel.4 p6dir.4 p6dir.4 p6out.4 dv ss p6in.4 unused p6sel.5 p6dir.5 p6dir.5 p6out.5 dv ss p6in.5 unused note: the signal at pins p6.x/sifchx and p6.x/sifcix are shared by port p6 and the san if module. p6sel.x must be set if the correspondin g pins are used by the scan if.
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 46 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p6, p6.3 input/output with schmitt-trigger p6in.3 module x in pad logic en d p6out.x p6dir.3 p6sel.3 sifcaout 0 1 0 1 bus keeper to/from scan i/f 0: input 1: output p6.3/sifch3/sifcaout p6sel.x must be set if the corresponding pins are used by the scan if. note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, if an analog signal is applied to the pin. p6sel.3 p6dir.3 port function 0 0 p6.3 input 0 1 p6.3 output 1 0 sifch3 (scan if channel 3 excitation output and comparator input) 1 1 sifcaout (comparator output)
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 47 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p6, p6.6 input/output with schmitt-trigger p6in.6 module x in pad logic en d p6out.6 p6dir.6 p6sel.6 dvss 0 1 0 1 bus keeper to scan i/f comparator input mux from scan i/f dac 0: input 1: output p6.6/sifci2/dacout 1 p6sel.x must be set if the corresponding pins are used by the scan if. note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, if an analog signal is applied to the pin. p6sel.6 p6dir.6 port function 0 0 p6.6 input 0 1 p6.6 output 1 0 sifci2 (scan if channel 2 comparator input) 1 1 sifdaout (scan if dac output)
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 48 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p6, p6.7 input/output with schmitt-trigger p6in.7 module x in pad logic en d p6out.7 p6dir.7 p6sel.7 dvss 0 1 0 1 bus keeper to scan i/f comparator (+) terminal to svs 0: input 1: output p6.7/sifci3/svsin svs vldx=15 1 svs vldx=15 p6sel.x must be set if the corresponding pins are used by the scan if. note: analog signals applied to digital gates can cause current flow from the positive to the negative terminal. the throughput current flows if the analog signal is in the range of transitions 0 1 or 1 0. the value of the throughput current depends on the driving capability of the gate. for msp430, it is approximately 100 a. use p6sel.x=1 to prevent throughput current. p6sel.x should be set, if an analog signal is applied to the pin. svs vldx = 15 p6sel.7 p6dir.7 port function 0 0 0 p6.7 input 0 0 1 p6.7 output 0 1 x sifci3 (scan if channel 3 comparator input) 1 x x svsin
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 49 post office box 655303 ? dallas, texas 75265 application information jtag pins tms, tck, tdi/tclk, tdo/tdi, input/output with schmitt-trigger or output tdi tdo tms tdi/tclk tdo/tdi controlled by jtag tck tms tck dv cc controlled by jtag test jtag and emulation module dv cc dv cc burn and test fuse g d s u g d s u tck tau ~ 50 ns brownout controlled by jtag rst /nmi
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 50 post office box 655303 ? dallas, texas 75265 application information jtag fuse check mode msp430 devices that have the fuse on the tdi/tclk terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current, i tf , of 1.8 ma at 3 v can flow from the tdi/tclk pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if the tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current only flows when the fuse check mode is active and the tms pin is in a low state (see figure 21). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). the jtag pins are terminated internally, and therefore do not require external termination. time tms goes low after por tms i tf i tdi/tclk figure 21. fuse check mode current, msp430fw42x
msp430xw42x mixed signal microcontroller slas383b ? october 2003 ? revised june 2007 51 post office box 655303 ? dallas, texas 75265 data sheet revision history literature number summary slas383b updated functional block diagram (page 3) clarified test conditions in recommended operating conditions table (page 18) clarified test conditions in electrical characteristics table (page 19) added i lkg(px.x) for all ports in leakage current table (page 20) clarified test conditions in dco table (page 29) changed t cpt maximum value from 4 ms to 10 ms in flash memory table (page 36) note: page and figure numbers refer to the respective document revision.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) msp430fw423ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430fw423ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430fw425ipm active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr msp430fw425ipmr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr MSP430FW427IPM active lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr MSP430FW427IPMr active lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-jan-2007 addendum-page 1
mechanical data mtqf008a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pm (s-pqfp-g64) plastic quad flatpack 4040152 / c 11/96 32 17 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min gage plane 0,27 33 16 48 1 0,17 49 64 sq sq 10,20 11,80 12,20 9,80 7,50 typ 1,60 max 1,45 1,35 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. may also be thermally enhanced plastic with leads connected to the die pads.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers 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